This section introduces aspects that may help facilitate a better understanding of the invention. Accordingly, the statements of this section are to be read in this light and are not to be understood as admissions about what is prior art or what is not prior art.
Serial high-speed data received by an SRIO endpoint contains both data packets and control symbols. This serial data is typically converted to parallel data by the SRIO receiver. In some applications, it is necessary to keep the start of packet (SOP) and start of control symbols (SOC) data aligned in the parallel data, where “alignment” means that the first bit of each instance of SOP or SOC data corresponds to the first bit of a parallel data word.
In one possible application, the parallel data consists of double 32-bit words (64 bits total), where clock tolerance compensation (CTC) processing can cause two 8-bit idle characters to be removed or inserted in the high-speed data stream. As known in the art, CTC processing compensates for a frequency differential that may exist between a local reference clock at the receiver and the data rate of the received serial data. This CTC processing can result in the SOPs and/or SOCs becoming misaligned by 16-bit increments with respect to the double-word boundary of the parallel data stream. In that case, circuitry is needed to correct for this misalignment resulting from CTC processing to ensure that the SOP/SOC data is properly aligned within the parallel data stream provided to downstream processing.